• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    1. A DEVICE FOR TRANSFORMING A BINARY CODE TO A MAGNETIC MEDIA CODE, containing an input converter and a shift register, the information inputs of which are connected to the outputs of the input converter, whose information inputs are connected to the information inputs of the device, the first clock input of which is connected to a time slot with a time slot to a slot. is the output of the device, it is necessary that, in order to expand the class of solvable tasks by ensuring the minimization of the constant component stored code sequences, a current difference calculation unit, a difference integrator consisting of an adder and a register, a group of EXCLUSIVE OR elements, a one-bit comparison circuit and a shift control unit containing two D triggers and an AND-NAND element, first and second the inputs of which are connected respectively to the inverse input of the first and direct output of the second D-flip-flop, the sync inputs of which are connected to the first clock input of the device, the second clock input of the clock is connected to the clock input of the register and The 0 input of the first) trigger, the direct output of which is connected to the D input of the second 1) trigger, the output of the NAND element is connected to the control input of the shift register, the additional information input of which is connected to the output of the one-bit comparison circuit. the input of the input converter and with the first inputs of the EXCLUSIVE OR elements of the group, the second inputs of which are connected respectively to the outputs of the higher bits of the computing unit for the current difference, the information inputs of which are connected respectively to the infor device inputs, and the low and high bits of the current difference calculator are connected to the low bits of the first group in: soda of the adder and g with the first input of the one-bit comparison circuit 00, the second input of the KOTOpofif | The high-order output of the register, the inputs of which are connected to the Nd outputs of the total curtain, the inputs of the higher-order bits of the first group of which are connected to the outputs of the elements EXCLUDE THE ELSE, the groups, the inputs zero and the unit of the current difference calculation unit are the outputs zero and units of the device, the outputs of the register are connected to the inputs of the second group of the adder. 2. The device according to A.1, about t l and that the input converter in it is complete in the form
    公开号:SU1148572A3
    申请号:SU803211254
    申请日:1980-11-03
    公开日:1985-03-30
    发明作者:Симада Тосиюки
    申请人:Сони Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    groups of elements EXTRA POSSIBLE OR, the first inputs of which are informational inputs of the input converter, the second inputs of elements EXCLUSIVE OR groups are connected to the control input of the input converter, and the outputs of elements EXCLUSIVE OR groups are the inputs of the input converter.
    3. The device according to claim 1, which includes the block for calculating the current difference, contains the subtractor and the first and second nodes for calculating the number of units, each of which consists of the element AND and the element EXCLUSIVE OR, the first and second inputs of which are connected respectively with the first and second inputs of the AND element and are informational inputs of the current difference calculating unit, the outputs of which are connected to the outputs of the subtractor, the carry and first discharge inputs of the first and second groups of which are connected to the input of the logical unit of the calculator Findings of current differences, the inputs of the second bits of the first and second groups of the subtractor are connected respectively to the outputs of the EXCLUSIVE GDI elements, the inputs of the third bits of the first and second groups of the subtractor are connected respectively to the outputs of the elements AND, sxot of the fourth bits of the first and second groups of the subtractor are connected respectively, with inputs zero and unit of the current difference calculation block.
    4. The device according to T, which is based on the fact that in it the one-bit comparison circuit consists of the EXCLUSIVE OR element and the output HEi of which is the output of the single-digit comparison circuit whose inputs are inputs EXTENSION OR OR, the output of which is connected to the input of the element NO.
    5. The device according to item 1 ,. Since it includes the input converter and the current difference calculator in the form of a permanent storage device, the lower-end address inputs of which are connected to the information inputs of the device, the high-end address input is an additional information input of the input converter, the outputs of which are connected to the group of outputs of the lower bits of the constant memory, the group of outputs of the higher bits of which are the outputs of the current difference calculator and.
    6. The device according to Claim 1, that is, in it the block for calculating the current difference contains a group of input elements NOT, a decoder of combinations with a difference other than + 1t two groups of elements НЁ-ШШ and a group of elements NOT, the outputs of which are The outputs of the higher bits of the current difference calculation block, the output of the first bit of which is connected to the input of the logical unit, the output of the group of the lower bits & current of the calculation of the current difference are connected to the outputs of the NE-IPI elements of the first group, the outputs of the NOT-OR elements of the second group are connectedthe inputs of the corresponding NOT elements of the second group, the inputs of the YE-OR elements of both groups are connected to the corresponding output groups of the decoder combinations with a difference other than +1, the first group of inputs of which is connected to the information inputs of the current difference calculation unit and the inputs of the input elements NOT groups whose outputs connected to the second group of inputs of the Combination Devshfratora with a difference other than -f 1.
    7. The device according to claim 1, wherein the current difference calculation unit contains a group of elements NOT, a NOT-OR element and a combination decoder with a difference of 2, the first group of inputs of which is connected to the information inputs of the current difference calculation unit and with the inputs of elements NOT groups, outputs; odes of which are connected to the second group of inputs of the decoder combinations
    with a difference of 2, the first output of which is the output of the higher bit of the current difference calculation unit, the output of the lower bit of which is connected to the output of the NOT-OR element, whose inputs are respectively connected to all the outputs except the first decoder of combinations with a difference of 2.
    The invention relates to digital computing and may be
    used in the construction of devices for converting information into codes used by magnetic media. five
    A device for converting a binary code into a magnetic carrier code is known, which contains two pulse generators, a modulator, an encoder, a Schmidt trigger, a for- interfacing pulse generator, two triggers with corresponding PJ connections,
    A disadvantage of the known device is the impossibility of tracking and minimizing the constant component of the code sequence.
    The closest to the present invention is a device for converting a binary code into a magnetic carrier code, containing an input converter and a shift register, the information inputs of which are connected from the output of the input converter, whose information inputs 1e are connected to information inputs of the device.
    The first clock input of which is connected to the clock input of the shift register, the output of which is the output of the device.
    In addition, the known device 30 includes a memory control, a decoding unit, a special character memory, and a counter.
    A disadvantage of the known device also consists in the impossibility of monitoring and minimizing the constant component of the code sequence.
    The purpose of the invention is to develop a class v problem of problem solving by ensuring the minimization of a constant composition of 40 liters to the actions of stored code sequences.
    The goal is achieved by the fact that the device for converting a binary code into a magnetic carrier code containing an input converter and a shift register, the information inputs of which are connected to the outputs of the input converter, the information inputs of which are connected to the information inputs of 1 device; The first clock input of which is connected to the clock input of the shift register, the output of which is the output of the device, has been entered .55 a block for calculating the current difference, the integrator of the difference, the states from the adder and the register, a group of elements.
    EXCLUSIVE OR, a one-bit comparison circuit and a shift control unit, containing two D-flip-flops and an IS-NOT element, the first and second inputs of which are connected to the inverse output of the first and direct output of the second D-flip-flops, the sync inputs of which are connected to the first clock the input of the device, the second Tai;: the input of which is connected to the clock input of the register and the D input of the first D-flip-flop, the direct output of which is connected to the D-input of the second D-flip-flop, the output of the AND input is NOT connected to the control input of the shift register up The complementary information input of which is connected to the output of a one-bit comparison circuit, with the control input of the input converter and the first inputs of EXCLUSIVE OR groups, the second inputs of which are connected respectively to the outputs of the higher digits of the calculation unit. The current difference, whose information inputs are connected respectively to the higher bits of the calculator. the information inputs of the device, and the low-order and high-order bits of the current difference calculation block are connected respectively to the low-end inputs of the first group The inputs of the adder and the first input of the one-bit comparison circuit, the second input of which is connected to the output of the high register register, the input of which is connected to the output of the adder, the inputs of the higher discharge bits of the first group of which are connected to the outputs of the EXCLUSIVE OR group, the inputs of zero and block units calculating the current difference; are the outputs zero and units of the device; the outputs of the register are connected to the inputs of the second group of the adder,.
    ; The input converter is completed; As a group of EXCLUSIVE OR elements, the first inputs of which are the information inputs of the input converter, the second inputs of the EXCLUSIVE OR elements are connected to the control input of the input converter, and the outputs of the EXTRACTOR OR groups are the outputs of the input converter.
    The unit for calculating the current difference contains the quantifier and the first and second nodes for calculating the number of units each of which consists of and
    This AND the EXCLUSIVE OR element, the first and the second, whose inputs are connected respectively to the first and second inputs of the EXCLUSIVE OR element, are the information inputs of the current difference calculator, the outputs of which are connected to the subtractor outputs, the transfer inputs and the first bits of the first and second Groups which are connected to the input of the logical unit of the current difference calculation unit, the inputs of the second bits of the first and second groups of the subtractor are connected respectively to the outputs of the elements EXCLUSIVE OR OR, the inputs of the third bit to in the first and second groups, the subtractors are connected respectively to the outputs of the AND elements, the inputs of the fourth bits of the first and second groups of the subtractor are connected respectively to the inputs of zero and the unit of the current difference calculation unit.
    The one-bit bottom of the comparison circuit consists of an EXCLUSIVE OR element and a NOT element whose output is the output of a one-bit comparison circuit whose inputs are the inputs of an EXCLUSIVE OR element whose output is connected to the input of the NO element.
    I .-
    The input converter and the current difference calculating unit are made in a permanently stored memory device whose address inputs of the lower bits are connected to the information inputs of the device, the address input of the high bit is an additional information input of the input converter, the outputs of which are connected to the output group of the low-voltage bits auxiliary device, the group of outputs of the higher bits of which are the outputs of the current difference calculation unit.
    The block for calculating the current difference contains a group of input elements NOT, a depesfraurator of combinations with a difference other than +1, two groups of elements. This is NOT-OR and a group of elements NOT which outputs are outputs. the higher bits of the current difference calculation block, the output of the first bit of which is connected to the input of a logical unit, the output of the group of digits of the current difference difference block of the block is connected to the outputs of the NOT-OR elements, the first group, the outputs of the NOT-OR elements of the second group;
    dinene with the inputs of the corresponding NOT elements of the second group, the inputs of the BE-IL elements of both groups are connected to the corresponding output groups of the decoder of combinations with a difference other than +1, the first group of inputs of which is connected to the information inputs of the current difference calculation unit, and the outputs of which are connected to the second group of inputs of the decoder combinations with a difference other than +1.
    The unit for calculating the current difference contains a group of elements NOT, the KE-4SH element and the decoder of combinations with a difference of 2; the first group of inputs of which is connected to the information inputs of the block from the current time. and with the inputs of the NOT elements of the group, the outputs of which are connected to the second group of inputs of the decoder of combinations with a difference of 2, the first output of which is the output of the higher bit of the current difference calculator, the output of the low-order bit of which is connected to the output of the element; , that is NOT-SHS, the inputs of which are correspondingly connected to all outputs, except the first one, of the combine, with a difference of 2.
    Fig. 1 graphically represents the five-bit pattern of digital signals i in Fig. 2 —codograms of sequences of words and voltage plots in Fig. 3: a block diagram of a first embodiment of the device for converting a binary code into a magnetic carrier code in Fig. 4; The shift register and the shift control unit in FIG. 5 are block diagrams of the second embodiment of the proposed device, fit 6. The logical circuit of the current difference calculation unit; figure 7 is a block scheme of the second embodiment of the proposed device; on Fig the same, of the third embodiment, figure 9-11 - skeletal schemes different. personal options for the implementation of the proposed device.
    An example diagram of one of the variants of the proposed device for an example of four-bit conversion. The input code in the five-bit output code (,) is shown in FIG.
    The device contains an input converter 1, a shift register 2, a current difference calculation unit 3, a one-bit comparison circuit 4, a difference integrator 5, a shift control unit 6 and a group of 7 elements EXCLUSIVE OR.
    Input converter 1 contains a group of 8 EXCLUSIVE OR elements, and a shift control unit 6 contains triggers 9-10 and an AND-NE element 11, the output of the shift register is the output 12 of the device, with the Bits ahead. Shift control unit 6 receives the first 13 and second 14 clock inputs of the sync pulse, the output of which is reflected in Fig. 4 (C, i)). Block 3 for calculating the current difference contains the tester 15 and the first 16 and second 17 nodes for calculating the number of units in kah-. Each of which includes the element AND 18 and the element EXCLUSIVE OR 19. The integrator 5 of the difference consists. from the adder 20 and the register 21. The one-bit pattern of the comparison circuit 4 contains the element JACK-ORDER 22 and e. COP NOT 23.
    Another BajJHaHT rvalis1C1I of the invention is presented in FIG. Here, in addition to the blocks indicated in FIG. there is a block 24 for comparing the difference with a constant, containing P-thrunger 25, elements AND-NOT 26-28, element NE-NSH 29 and element NOT 30. D-trigger 25 is designed to store the value of the highest bit of the difference of the preceding word in the input word. The output of the non-INR element 29 is connected to the input of the one-bit comparison circuit 4 for comparison with the high-order bit of the difference of the preselected code word ..
    j Another embodiment of the current difference calculation unit, which can be used in any of the two described structural diagrams of the device proposed, is presented in FIG. This block contains a group of input elements NOT 31, a deshator for 32 combinations with a difference other than +1, the first 33 and the second 34 groups of elements NOT-OR and a group of elements NOT. This option is a two-dimensional I-SHSh combination scheme, but in accordance with the methods of synthesis of combination schemes.
    it can be implemented in a multi-light combinational circuit.
    An embodiment of the proposed device implementing the transition table 2 is shown in Fig. 7. The current difference calculation block contains a combination decoder 35 with a difference of 2 and a NOT-OR element 36, the first 37 and a second 38 elements EXCLUSIVE OR. The parity block 39 contains the elements AND- NOT 40-43, the element is NOT-OR 44 and the element is EXCLUSIVE ШШ 45. The proposed device can be built (Fig. 8) using the reversible counter 46 as a difference integrator. In this case, a third clock input 47 of the device connected to the counting input of the reversing counter 46 is required.
    Figures 9-11 show the structural diagrams of various embodiments of the device proposed, each of which includes an n / m-bit input converter 1, shift register 2 and a selector 48 of the codeword. In each of the variants of the n-bit information word is transmitted to converter 1 in parallel. The converter is intended to translate each p-bit of a word into its corresponding ha-bit code word, and it is transmitted in parallel to the shift register 2, which performs the sequential output of the t-bit word. The selector 48 generates an Sg signal, which is used for a positive or negative codeword consisting of m bits, and contains a current difference calculation unit 3, a one bit comparison circuit 4, and a difference integrator 5.
    The proposed device works as follows.
    Figure 1 shows an example of a five-bit code word for which. If binary 1 is represented by a positive, and negative negative voltage level, then when transmitting a sequence of words, a constant voltage component will arise, depending on the difference in the number of units and zeros transferred.
    We will call the difference DSP value
    DSP-n -no (1)
    - the number of units contained in the digital word,
    -number of zeros, the same digital word.
    t-bit codeword
    . Therefore, the difference m. The expression of the variation of the digital sum refers to the magnitude of the constant component obtained by integrating consecutive binary ones and zeros of consecutive digital signals, for example, consecutive t-bits of the elephant code. If digital words are transmitted in sequential code, the magnitude, variations of the digital sum, changes with each subsequent binary bit. For example, the variation of the digital sum of the successively transmitted word (10010) varies sequentially from the initial value (for example, from zero) in the following way: +1, O, -1.0 At the end of the word, it will take the value -1. Otksccha follows that the difference of the considered word (10010) is equal to -1. In this way, the difference for the set of t-bit code words is calculated, which represents the constant component of these words. The code words are chosen so that the magnitude of the total variation. digital sum was minimal. When transmitting a sequence of information or code words without restricting their choice,
    when the variation of the digital sum for a sequence of such digital words will increase indefinitely in positive or negative directions. However, in accordance with the invention, the maximum value of the variation of the digital sum is set, and the definition of the t-bit codewords is made so that the total value of the variation of the digital sum is reduced.
    Table 1 presents five-bit code words with positive and negative difference for each four-bit information word. In addition, this table provides a numerical representation of the positive and negative differences, with negative values represented as additional code. Thus, the information word (0000) can be represented either by a code word (00000) referred to in Table 1 to the number of code words with a + sign, or by means of a code word (11111), referred to as a code word with a-sign. The difference of the code word with the + sign is -5, and the Chi representation of the difference -5 as an additional code to two is (101.1). The magnitude of the difference of the code word with a sign is equal to +5, which is numerically represented as - (0101).
    Suppose you want to encode the following sequence of information words: (0000), (0001), (0010), (0011), (0100). These sequences (Fig. 2) are represented in successive periods of time Tj ,, T-, Tj, Ti, 2 and -T, respectively. Fig. 2B shows the difference for each code fame in Fig. 2, the selection of a specific code word that is used to represent the corresponding information word; in Fig. 2E, a waveform image for the variation of the digital sum, which is calculated for each consecutive binary bit. select coding words.
    From Fig. 2, it is seen that, when encoding the next information word, the variation of the digital sum, which was calculated for the preceding code words, is taken as the basis. If the amount of variation of a digital sum has a positive sign, then the information word being encoded is represented by a code word having a negative difference. Conversely, if the calculated digital variation has a negative 1st digit, then the information word is represented by a code word having a positive difference. This means that in the considered example the maximum value of the variation of the digital sum is limited to i5.
    The input information word (Fig. 4) is fed to the inputs of the input converter 1, which in the case under consideration forms a parallel five-bit code word for each input four-bit information word, and the value of the higher bit of the output tree is determined by the selection signal Sg . If its value is O, then the remaining bits of the code word are respectively equal to four binary bits of the input word. The values of the remaining four bits of the code word are additions to the corresponding bits of the input word, i.e. As a result of the operation of the input transducer 1, coded words are formed with a + or - sign,
    The output Q of the shift register is a typed code word.
    in sequential code, high-order ahead.
    The timing diagrams of the operation of the shift register 2 and the shift control unit are shown in FIG. 4.
    The sequence of input words is transmitted to the input converter in successive periods of time T-,, Tj-, etc. Fig. 4B shows the formation of five-bit code words, each word being transmitted to the corresponding inputs A-E of the shift register 2.
    Synchronized pulses CK1, CK2 are shown in FIG. 4C 4D, and the pulses CK2 have a frequency that is five times higher than the frequency of the pulses CK1. The D-flip-flop state 10 monitors the state of the control clock (FIG. 4E), and the B-flip-flop 9 monitors the D-flip-flop state 10 with a delay of His one period of the CK2 shift pulse.
    Element 1 generates a shift control signal (1) or a write signal (0). As shown in FIG. AN, a five-bit code word in a parallel code transmitted to the inputs A-E of the shift register 2 at the time of generating a binary input signal equal to O is entered into the shift register and then sequentially shifted to the output Q synchronously with the arrival of each pulse CK2, with a single value of the input L.
    Block 3 for calculating the current difference is designed to calculate the difference between each five-bit code spruce. From table 1 it follows that the difference of the code word can be determined on the basis of the input word. Nodes 16 and 17 count the number of units contained respectively in the first and second pairs of bits of the input word Subtractor 15 is designed to double the counted number of binary units and subtract the number 5 from it if 1 does not contain any of the two bits coming into the node 16, then both elements (AND, EXCLUSIVE OR) form binary zeros. If there is only one binary 1 in a pair of binary bits, then the EXCLUSIVE OR element forms a binary 1 at the output, while the output of the And element forms a binary O.
    111
    : ia, the shift of the codes at the inputs of the reader 15 and the job and the zeros at its outputs is calculated by the difference value, represented as a four-digit number at the outputs 2 (j, T ,, 2, and the high bit in this digital representation is transmitted to the output Z. The low-order bit in the output is always binary 1. The highest bit of such a positive code word is O, and the indicated high-bit bit is equal to the selection signal S. Thus, the result obtained is correct if the input word is encoded as positive. like a trace According to Table 1, if the input word is encoded as negative, then the sign of the difference above should be inverted.The digital representation formed by the subtractor 15 corresponds to the difference of the positive word. If the information word is negative, the high bit is 1 and the selection signal (S), the digital representation generated at the outputs of the subtractor is modified. In particular, from table 1 it is seen that the absolute value of the difference of positive and negative code words that are They are used to represent the same information word, the same, but the signs of these differences are opposite, i.e. difference of each positive
    The codeword is an addition to two for the difference of a negative codeword. This operation is performed by a group of EXCLUSIVE OR 7 elements in accordance with the state of the selection signal S, which is equal to O when a positive word is selected (the EXCLUSIVE OR elements 7 skip bits Zi - 3 without changing) and is equal to a binary one when a negative code word is selected ( the elements EXCLUSIVE OR 7 form an addition for the values of bits). Binary 1 is generated at the output, for all digital representations of positive codewords remains unchanged, regardless of whether the selection signal is SK O or 1. This is due to the fact that the calculated difference is an odd number that requires so that the smallest sign 72 12
    Chipdiy dvonchmp razd in esh 1i1froium representation bych is equal to 1.
    The output signals of the EXCLUSIVE 1E OR 7 elements, together with the signal generated at the output T of the subtractor 15, form a digital representation of the difference calculated for the codeword, which is used to represent the input word, the most significant bit indicating the sign of the difference, and the remaining bits representing In digital form, the absolute value of this difference. : I
    The EXCLUSIVE OR 22 element compares the sign of the variation of the digital sum calculated for the preceding code words with the positive code word sign by which the encoded information word is represented. If the difference sign (output) is equal to the digital sum variation sign (register output 21), then the output of the EXCLUSIVE IL 22 element is O, and vice versa, if the difference signs and variations of the digital sum differ from each other, the EXCLUSIVE OR 22 element forms by its output unit, which is inverted by inverter 23 to form selection signal Sj equal to binary O. At the initial moment of time, the one-bit comparison circuit 4 controls the operation of the input converter in such a way that a positive code word is selected. If the difference of the selected positive code word can lead to an increase in the variation of the digital sum, the preselection is replaced with the opposite one and a negative code word is entered into the shift register. After the correct choice of the code word, the variation value of the digital sum is updated. This means that the variation of the digital sum, which is defined as a function of the preceding code words, is updated so that it additionally takes into account the currently selected code word transmitted in the sequential code from the output of the shift register.
    In particular, the new value of the variation of the digital sum is determined by summing the variation of the 1 and tfra sum calculated for the nc-dkkeptv code words, with the difference tt following the next code word entered in the shift register 2. For this, five inputs are transmitted to the inputs A of the adder 20. the bit code is the difference, and the B input is the code of the current variation of the digital sum. At the outputs Z, Z,, Sj and 3 of the adder 20, a four-bit code of the new variation of the digital sum is generated, which is transmitted to the inputs IQ, I,, 1 and I, of the register 21. In another embodiment of the device (FIG. 5) block 24, designed to determine whether the current value of the variation of the digital SUM is equal to the specified value and (if such a fact is established) to control the choice of the next code word in order to minimize the working length. The AND-NE element 26 decrypts the state of the register 21, for example, the value (0000). The trigger 25 temporarily stores the state of the most significant bit of the difference of the preceding codeword. The information is recorded by synchronizing with a scan pulse CK1 at the time the specified code word enters from the shift register 2. When memorizing a new variation of the digital sum in register 21, the most significant bit of the difference is stored in. D-trigger. 25 Block 24 is driven by an AND-NE element 26 to transmit the old one. This is the difference of the previous code word stored in trigger 25 in comparison circuit 4 for comparison with the highest bit of the calculated difference of the selected code word. This transfer is carried out by the 26th and 26th .. blots. Let the subsequent information word be 1100, and the difference of the reference code word is -1. The digital representation of this difference is (1111). Since the variation of the digital sum stored in register 21 is +1 AND-NOT 26 forms 1, i.e. the prohibition of the H-NE-28 element for transmission 1 stored in the trigger 25. But this same signal permits the NE-27 element to transmit the highest bit stored in the register 21. Because (by condition) the memory stored in the digital variation the sum equals +1, which is represented numerically in the form 0001, then the most significant bit of this variable is equal to binary O. This bit is 72 O and is transmitted to the input of the AND-NE 27 element, where it is inverted and fed to the PE-OR 29 element. The calculated difference is represented in digital form as (1111), whence it follows that the value of the most significant bit is This difference is different from the most significant bit stored in register 2. Therefore, in this case, the comparison circuit 4 generates a select signal equal to binary O at its output. In accordance with this signal, a positive code word is entered into the shift register 2 It looks like 1 01100). In addition, the binary 1 of the most significant bit of the calculated difference is stored in the trigger 25. At the inputs A of the adder 20 a negative unit is transmitted (AND 11), and the input B is a positive unit (0001). The adder performs the addition of the difference of the selected codeword with the current value of the variation of the digital sum. As a result of this addition, the new variation value of the digital cjTMMM is reduced to zero and is stored for storage in register 21. Now let the digital representation of the input word be (001t). ; In the first embodiment of the device (FIG. 3), since the current value of the variation of the digital sum is zero, the information word (0011) is represented as a positive code word. The immediately preceding code was (01100), the sequence of binary zeros begins in this case: from the succession of two zeros of the preceding code word and occupies the first three binary zeros of the subsequent code word. Such a length may adversely affect the self-synchronization of a code word. In accordance with the variant shown in FIG. 5, instead of a positive code word, in this case, a negative codeword is selected. : In particular, the current value of the variation of the digital sum (EOSU) is fixed by the AND-PE element 26, from the output of which comes O, which prohibits the AND-HE element 27, which blocks the comparison of the binary bit of the order stored in the register 21, the sign of the calculated difference. In addition, the element NOT 30 prepares the operation of the element AND-NOT 28. Binary 1 stored in trigger 25 and represented as (1111), in the form of binary 1, enters through the elements 28-29 to the input of the comparison circuit, to the other input which arrives bit sign of the difference of the positive code word used for the input word (0011). Therefore, units are supplied to both inputs of the comparison circuit 4, O is generated at the output of element 22, which leads to the formation of a single selection signal S. Therefore, instead of selecting a positive code word (00011) which would lead to an undesirable increase in the length of binary zeros, a negative code word (11100). Thus, to prevent undesirable length, if the current value of the variation of the digital sum is zero, a code word is selected to represent the next information word, the difference of which has opposite sign to the difference sign of the immediately preceding code word (otherwise the same). Logic block 3 computations. Neither the current difference (Fig. 6) can be used in both versions of the device proposed (Fig. 3.5). Decoder 32 determines whether. 1 72 the coded word to one of the given information words, and encrypts with the help of the elements NOT-OR 33, 34 the difference code. In accordance with a different encoding method, each positive codeword has a positive difference, and each negative codeword has a negative difference. Table 2 lists the positive and negative code words that are used to represent each information word, along with the corresponding difference (and the digital representation of this difference) of each code word. Table 2 differs from Table 1 in that the most significant bit of a positive code word can take the value 1 or binary O, while the most significant bit of each positive code word in table. can be only zero. The difference of each positive code word in Table 2 is positive, whereas in Table 1 the difference of a positive code word can be both positive and negative (depending on the particular configuration of Binary bits in the code word). An embodiment of a device that can be used to encode an input word into a codeword in accordance with Table 2 is shown in FIG. 7.
    11111
    11110 11101 11100 11011 11010 1 1001
    Table 2 Each of the outputs of the decoder 35 is designed to identify the input information word among the specified groups of words. Element HLE-OR 36 forms output 1 if the input information word is equal to one of the five pre-defined words. The inputs of the FALSE OR elements 37-38 are connected together to receive the inverted high order value of the variation of the digital sum stored in the register 21. The outputs of the element NO 23, the elements EXCLUSIVE OR 37, 38 correspond to the three most significant bits of the calculated codeword difference, which is used for the representation of the input word, and the least significant difference bit is 1. The learned four-digit digital representation of the calculated difference is transmitted to the inputs A of the adder 20, to the inputs B which is supplied with the digit ovo digital representation sumGTorogovsh variation unit 39 is designed to determine whether an input word comprises three or more units. In particular, the AND-NOT element 40 is intended to determine whether the input information word is a word (0111). The elements AND-NO 40-43 are triggered when the input word (1111) is used. The output of the NE-IL element 44 is a signal 1, when any of the specified pre-defined information words is received. The output of this element is compared to the highest bit of the variation of the square sum amount stored in register 21 by means of the EXCLUSIVE OR 45 element whose output signal is used as the high bit of the code word, depending on the value of this output signal (1 or 0) the remaining four bits of the code word in this case are inverse or. direct values of the input information word. The interaction of the threshold block 39 with the input converter 1 leads to the formation of a negative code word, the highest bit of the second is O, and which has a negative difference if the variation value of the digital sum is positive in all cases except when the input information word corresponds to one of these separate states. In this case, the old-order bit of the negative code fishing is changed to 1. Similarly, the threshold unit 39 controls the input transducer to form a positive code word. The input transducer 1 and the current difference calculator can be implemented on a permanent storage device, which can also be used to implement the functions of the threshold unit 39. The permanent storage device can contain, for example, thirty-two addressable memory cells of eight-bit words, and binary bits Djj-D represent a five-bit code word, and the remaining three bits are reserved for the three higher bits of the digital representation of the difference. To address each cell, a five-bit word can be used that goes to the address inputs. Starry bits of the address word may represent a variation sign of the digital sum. The rest of the address word word has been set aside to display a four-bit information word. If Table 2 is implemented, then all times, when the digit of the digit number is O, the cells that contain the negative code words are addressed, and the specific address of the memory cell is specified by the information word itself. Thus, the determined code word read from the ROM is an exact representation of the received information word at the input, and is selected as a function of the sign of the current value of the variation of the digital sum. In addition, in this same memory cell, three out of four bits are stored, representing the difference of the indicated code word. The difference integrator 5 in the proposed device can be executed on a reversible counter (Fig. 8), with
    000000000 000000001 000000010 000000011
    9 (01001)
    P1111111 7 (00111) 111111110 7 (00111) 111111101
    5U101) 111111100 than the block for calculating the current difference in this case can be omitted. Counter 46 integrates the binary units of the code words, which are sequentially and bitwise shifted from the shift register 2. Thus, the intermediate counting result contained in the counter at the given time is a variation of the digital sum of the previously transmitted code words. If we consider in more detail, we can say that binary input aa from the output of the shift register 2 to the output is controlled. Neither the counting direction of the counter 46 permits an increase in the number stored at this time in this counter upon receipt of each clock of the RMS. Conversely, a binary, subtending to the output control of the counting direction, allows the result of counting the counter to be reduced as each clock pulse arrives. The synchronization pulses of the RMS are the inverse values of the above described synchronization of the pulses of the CK2, with each synchronization pulse of the RMS synchronized with the transmitted binary bit of the COD9VO word. At the end of the shift of the entire code word, the most significant bit of the content of the reversible counter 46 represents the sign of variation of the digital sum, i.e. determines if the variation is digital, the sum is positive or negative. Similarly to the devices described, devices can be constructed for converting eight-bit words to nine and ten-bit ones. Transition tables for them are Table 3 and 4. Table 3
    Following table 3
    The results of choosing a particular code word to represent the input information word depending on the current variation of the digital sum are summarized in Table 5. It is assumed that five types of code words are acceptable: 1) each information word can be represented by a code word, having a zero pasHOCTbJ 2) each information word is represented by a code word with a zero difference and another code word having a positive difference 3) each the information word is represented by a code word with a zero difference and another code word having a negative difference, 4) each information word is represented by a code word with a positive difference and another code word m word having a negative difference; 5) each information word is represented by a code word with a positive difference
    Continuation of table 4
    another code word with a zero difference And another code word having a negative difference. The X character indicates which of these code words is selected if the value is current. The digital total sum (VCS) is positive, negative or zero.
    Table 5
    + VTSS
    -VTSS
    about VCS
    X x
    X x
    X
    X
    X
    X x
    X x
    X x
    l
    X
    X
    The block diagrams shown in Figs. 9, 10 and 11 contain a n / m-bit input converter 1 of the code, a shift register 2, and a code word selector 48. In each of the embodiments, the information is transmitted to the converter 1 in parallel code. The input converter is intended to translate the p-bit information word into I its corresponding m-bit code word, and the specified w-bit code word is transmitted in parallel. The main code is the shift register 2, which sequentially transmits the t-bit code 4 words. In addition, each code word selector generates a selection signal S, which is used to select a positive OR negative code word. Sedactor 48 contains a block of the current difference, a one-bit comparison circuit, and a difference integrator. As shown in FIG. 10, the codeword selector 48 is connected to the output of the shift register 2 and comprises a difference integrator shown in FIG. S. In the embodiment represented in FIG. 11, the t-bit code word generated by the input transducer 1 is transmitted to the code word selector 48, and in accordance with this code word, the specified selector generates a selection signal S. The code word selector contains a block 3 calculations of the current difference and integrator 5 differences shown in p. 7. In the embodiments of FIGS. 9-11, blocks 24 may be provided for comparing the difference with a constant (for example, such as shown in FIG. 5) to limit the undesirable length of binary zeros or ones in cases where the current variation value of the digital the sum is equal to the predetermined value, for example, zero. In addition, it was assumed that the difference is equal to the number of binary units contained in the codeword, minus the number of binary zeros contained in this word. If it is not necessary, the difference can be calculated as a function of the binary code, using a binary number minus the number of binary units contained in the code word.
    h / -f
    sh
    J - g: -y.4
    9 to 999
    Jbjv
    ; f 7f if
    / rJ J,
    d№
    Miff.
    w
    fM
    91 t
    Off in
    9 9 t 0
    9 99 t I
    .. -if;

    f f Of t
    t ft 90
    : -.jj. ; t
    9
    9№
    JXP P-1Tfn l Y (OOP O) yCW 00 and (O O 1 g (g / 1 f
    & Qn -H Hz: I / g ff & 0 t wholesale gjxr / 1 t о f) yC / / / eJT
    GG "
    权利要求:
    Claims (7)
    [1]
    1. A device for converting a binary code into a magnetic carrier code, comprising an input converter and a shift register, the information inputs of which are connected to the outputs of the input converter, the information inputs of which are connected to the information inputs of the device, the first clock input of which is connected to the clock input of the shift register, the output of which is the output of the device., characterized in that, in order to expand the class of tasks to be solved by ensuring minimization of the constant component of storage code sequences, the current difference calculation unit, the difference integrator, consisting of an adder and a register, an EXCLUSIVE OR group of elements, a one-bit comparison circuit and a shift control unit containing two B-triggers and an AND-NOT element with the first and second inputs of it are introduced into it respectively connected to the inverse input of the first and direct outputs of the second B-flip-flops, the sync inputs of which are connected to the first clock input of the device, the second clock input of which is connected to the clock input of the register and to the D-input of the first -th B-flip-flop, the direct output of which is connected to the O-input of the second D-flip-flop, the output of the NAND element is connected to the control input of the shift register, the additional information input of which is connected to the output of a single-bit comparison circuit, with the control input of the input converter and with the first inputs of the elements EXCLUSIVE OR groups whose second inputs are connected respectively to the outputs of the upper bits of the current difference calculation unit, the information inputs of which are connected respectively to the information inputs of the device -keeping, and outputs Jr. and "MSB current difference calculation unit respectively connected to the inputs of the first group of LSB adder inputs and a first input of a single-bit comparison circuit, a second input of which connected to the output of the highest bit of the register, the inputs of which are connected to the outputs of the adder, the inputs of the highest bits of the first group of which are connected to the outputs of the elements EXCLUSIVE, MORE OR groups, the inputs of zero and the unit of the calculation unit of the current difference are the outputs of zero and the unit of the device, the outputs of the register are connected to the inputs second adder group. x
    [2]
    2. The device according to claim 1, characterized in that in it the input converter is made in the form of a SU 1YU 1148572 group of 'elements EXCLUSIVE OR, the first inputs of which are informa-. the input inputs of the input converter, the second inputs of the elements EXCLUSIVE OR groups are connected to the control input of the input converter, and the outputs of the elements EXCLUSIVE OR groups are the outputs of the input converter.
    [3]
    3. The device according to claim 1, wherein the current difference calculating unit comprises a subtractor and first and second nodes for calculating the number of units, each of which consists of an element AND and an element 15 EXCLUSIVE OR, the first and the second inputs of which are connected respectively to the first and second inputs of the element And are information inputs of the current difference calculation unit, the outputs of which are connected to the outputs of the subtractor, the transfer and first inputs of the first and second groups of which are connected to the input of the logical unit unit calculating 1 of the current difference, the inputs of the second bits of the first and second groups of the subtractor are connected respectively to the outputs of the elements EXCLUSIVE OR, the inputs of the third bits of the first and second · groups of the subtractor are connected respectively to the outputs of the elements AND, the inputs of the fourth bits of the first and second groups of the subtractor are connected, respectively with inputs of the zero th unit of the current difference calculation unit.
    [4]
    4. The device according to claim 1, with the fact that in it a one-bit comparison circuit consists of an EXCLUSIVE OR element and an element NOT whose output is the output of the one-bit comparison circuit, the inputs of which are inputs of the EXCLUSIVE OR element, whose output is connected to the input of the element NOT.
    "
    [5]
    5. The device according to claim 1, characterized in that the input converter and the current difference calculating unit are made in the form of read-only memory, the address inputs of the least significant bits of which are connected to the information inputs of the device, the address input of the highest digit is additional the information input of the input converter current difference.
    [6]
    6. The device according to claim 1, wherein the current difference calculating unit contains a group of input elements NOT, a decoder of combinations with a difference other than + C, two groups of non-IPI elements and a group of elements NOT, the outputs of which are the outputs of the higher bits of the current difference calculation unit, the output of the first bit of which is connected to the input of a logical unit, the output of the group of lower orders ; the current difference calculation unit is connected to the outputs of the NOT-OR elements of the first group, the outputs of the NOT-IPI elements of the second group are connected to the inputs of the corresponding elements of the NOT second group, the inputs of the NOT-IPI elements of both groups are connected to the corresponding output groups of the decoder combinations with a difference other than +1 , the first group of inputs of which is connected to the information inputs of the unit for calculating the current difference and with the inputs of the input elements NOT groups whose outputs are connected to the second group of inputs of the decoder combinations with different Stu different from one.
    [7]
    7. The device according to claim 1, characterized in that the current difference calculating unit contains a group of NOT elements, a NOT-OR element and a combination decoder with a difference> 2, the first group of inputs of which is connected to the information inputs of the current difference calculation unit and the inputs NOT elements of which are connected to the input path of the decoder with a difference> 2, the first go is the output of the highest bit of the current difference calculation unit, the output of the least significant bit of which is connected to the output of the NOT-OR element, the inputs of which are respectively connected to EMI outputs except the first decoder combinations difference} 2.
    group, the second group combination exit which’’’s 1148572 1
    类似技术:
    公开号 | 公开日 | 专利标题
    SU1148572A3|1985-03-30|Device for converting binary code to magnetic medium code
    US4115768A|1978-09-19|Sequential encoding and decoding of variable word length, fixed rate data codes
    RU2153707C2|2000-07-27|Method for converting m-bit data word sequence into modulated signal, record medium manufacturing process, encoder, decoder, recorder, reader, record signal and medium
    US4675650A|1987-06-23|Run-length limited code without DC level
    CA1193016A|1985-09-03|Method and apparatus for n-to-m encoding
    US3995264A|1976-11-30|Apparatus for encoding and decoding binary data in a modified zero modulation data code
    US3810111A|1974-05-07|Data coding with stable base line for recording and transmitting binary data
    JP3406440B2|2003-05-12|Pulse modulation method, pulse modulation device, and pulse demodulation device
    US4547890A|1985-10-15|Apparatus and method for forming d.c. free codes
    GB2098432A|1982-11-17|Consecutive identical digit suppression system
    EP0059224B1|1986-12-03|System for coding and decoding binary data
    KR920005361B1|1992-07-02|Digital data conversion method and apparatus
    US3906485A|1975-09-16|Data coding circuits for encoded waveform with constrained charge accumulation
    US5309156A|1994-05-03|Variable-length code decoding device
    KR100573626B1|2007-04-25|Apparatus and method for converting a sequence of m-bit information words into a modulated signal
    KR950010213B1|1995-09-11|Digital code converter apparatus and method
    US4425562A|1984-01-10|Device for coding signals which are distributed between a number of channels
    EP0193592B1|1991-11-13|Method and apparatus for processing digital signals prior to recording
    KR100529807B1|2006-02-01|How to convert a sequence of m-bit information words into a modulated signal, record carrier generation method, coding device, decoding device, recording device, reading device, signal and record carrier
    KR100448282B1|2004-09-10|Method for balanced encoding and decoding of locks having the different constant weight
    US3909781A|1975-09-30|Method of code conversion of messages
    US3478163A|1969-11-11|Reduced time transmission system
    GB1518997A|1978-07-26|Methods of and apparatus for representing digital data by electrical signals
    KR850001689B1|1985-11-22|Method for incording digital data
    EP0499225A2|1992-08-19|Variable-length code decoding device
    同族专利:
    公开号 | 公开日
    ZA806196B|1981-09-30|
    DE3039726C2|1987-05-14|
    GB2066629B|1984-10-24|
    ATA536080A|1994-10-15|
    NL8005999A|1981-06-01|
    DE3039726A1|1981-05-14|
    AU533027B2|1983-10-27|
    SE452537B|1987-11-30|
    US4499454A|1985-02-12|
    JPS6367268B2|1988-12-23|
    IT8025717D0|1980-10-31|
    GB2066629A|1981-07-08|
    BR8007071A|1981-05-05|
    CA1193015A|1985-09-03|
    SE8007667L|1981-06-18|
    FR2469047B1|1986-03-28|
    CH638646A5|1983-09-30|
    FR2469047A1|1981-05-08|
    JPS5665314A|1981-06-03|
    AU6389980A|1981-05-07|
    IT1188868B|1988-01-28|
    AT399627B|1995-06-26|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US3405235A|1963-03-12|1968-10-08|Post Office|Systems for transmitting code pulses having low cumulative displarity|
    US3521274A|1966-12-29|1970-07-21|Nippon Electric Co|Multilevel code signal transmission system|
    GB1156279A|1967-12-20|1969-06-25|Standard Telephones Cables Ltd|Data Transmission Terminal|
    NL136990C|1968-07-12|
    GB1250908A|1968-12-13|1971-10-27|
    GB1540617A|1968-12-13|1979-02-14|Post Office|Transformation of binary coded signals into a form having lower disparity|
    NL143770B|1969-02-25|1974-10-15|Nederlanden Staat|SCHEME FOR SENDING GROUP SIGNS WITH CONSTANT EMPLOYMENT RATIO.|
    US3753113A|1970-06-20|1973-08-14|Nippon Electric Co|Multilevel code signal transmission system|
    JPS5013046B1|1970-07-31|1975-05-16|
    US3796956A|1970-12-23|1974-03-12|Fujitsu Ltd|Block synchronization system of multinary codes|
    NL155149B|1972-05-04|1977-11-15|Nederlanden Staat|SCHEME FOR CONVERSION OF SIGNS ACCORDING TO A TWO VALUE CODE INTO SIGNS ACCORDING TO A TRIAL CODE.|
    GB1423776A|1973-02-08|1976-02-04|Standard Telephones Cables Ltd|Error detection in pcm systems|
    JPS5842668B2|1974-12-04|1983-09-21|Hitachi Ltd|
    GB2016247B|1978-03-04|1982-03-31|Plessey Co Ltd|Method of signalling supervisory information in digital line transmission systems|
    GB1569076A|1978-05-18|1980-06-11|Plessey Co Ltd|Digital transmission system using discrepancy line coding|
    JPS6226102B2|1979-10-27|1987-06-06|Nippon Telegraph & Telephone|JPS57176866A|1981-04-24|1982-10-30|Sony Corp|Encoder of binary signal|
    JPH0544206B2|1981-05-26|1993-07-05|Sony Corp|
    JPS5894114A|1981-12-01|1983-06-04|Matsushita Electric Ind Co Ltd|Binary information encoding system|
    NL8203619A|1982-09-20|1984-04-16|Philips Nv|A method for recording a digital information signal on a record carrier, a record carrier provided with such an information signal and a device for reading out such a record carrier.|
    US4486740A|1982-12-06|1984-12-04|At&T Bell Laboratories|DC Cancellation in ternary-coded data systems|
    US4598326A|1983-10-18|1986-07-01|Honeywell Inc.|Digital recording apparatus with disparity reducing encoder|
    JPH0683271B2|1983-10-27|1994-10-19|ソニー株式会社|Information conversion method|
    JP2559354B2|1984-02-24|1996-12-04|株式会社日立製作所|Digital signal modulation method|
    EP0158035B1|1984-03-09|1991-01-23|ANT Nachrichtentechnik GmbH|Circuit arrangement for determining the digital sum value of a digital data signal|
    US4833471A|1984-03-26|1989-05-23|Canon Kabushiki Kaisha|Data processing apparatus|
    DE3510724C2|1984-03-26|1990-12-13|Canon K.K., Tokio/Tokyo, Jp|
    FR2570905B1|1984-05-23|1987-01-09|Cit Alcatel|METHOD FOR SYNCHRONOUS DATA TRANSMISSION AND DEVICE FOR IMPLEMENTING SAME|
    NL8403078A|1984-10-10|1986-05-01|Philips Nv|METHOD FOR TRANSFERRING INFORMATION, CODER FOR APPLICATION IN THE METHOD AND DECODER FOR APPLICATION IN THE METHOD|
    US4649298A|1985-01-09|1987-03-10|At&T Bell Laboratories|Non-saturating tri-state driver circuit|
    FR2589653B1|1985-11-05|1990-03-23|Lignes Telegraph Telephon|DEVICE FOR IMPLEMENTING AN ACCUMULATED LOW DISPARITY CODE IN HIGH-SPEED DIGITAL TRANSMISSION AND CODING METHOD USING SUCH A DEVICE|
    NL8601603A|1986-06-20|1988-01-18|Philips Nv|CHANNEL CODING DEVICE.|
    US4775985A|1987-04-06|1988-10-04|Sony Corporation|Method of dc-free 8/9 nrz coding using a unique sync word pattern|
    EP0310041A3|1987-09-28|1990-08-22|Nec Home Electronics, Ltd.|8-bit to 9-bit code conversion system and 8/9 converter|
    JPH0233221A|1988-07-22|1990-02-02|Matsushita Electric Ind Co Ltd|Code converter and decoder|
    FR2664765B1|1990-07-11|2003-05-16|Bull Sa|DEVICE FOR SERIALIZATION AND DESERIALIZATION OF DATA AND SYSTEM FOR DIGITAL TRANSMISSION OF SERIAL DATA THEREOF.|
    NL9002772A|1990-09-21|1992-04-16|Philips Nv|DEVICE FOR RECORDING A DIGITAL INFORMATION SIGNAL IN A RECORD CARRIER.|
    NL9002070A|1990-09-21|1992-04-16|Philips Nv|DEVICE FOR RECORDING A DIGITAL INFORMATION SIGNAL IN A RECORD CARRIER.|
    JP2691480B2|1991-05-20|1997-12-17|富士通株式会社|Disparity detection circuit in 2B4B code rule inverse conversion|
    EP0557130B1|1992-02-19|2000-05-17|Mitsubishi Denki Kabushiki Kaisha|Data conversion method and recording/reproducing apparatus using the same|
    GB2267416B|1992-05-27|1995-09-20|Sony Broadcast & Communication|Coding of digital signals|
    KR0141126B1|1992-08-31|1998-07-15|윤종용|Cord converting controller and method in the digital recording/reproducing apparatus|
    US5805632A|1992-11-19|1998-09-08|Cirrus Logic, Inc.|Bit rate doubler for serial data transmission or storage|
    US5341134A|1992-12-30|1994-08-23|Datatape Incorporated|Simple coding scheme for DC free channel codes of form M/N, where M=N-1 and M and N are positive integers|
    JP3240341B2|1993-07-06|2001-12-17|三菱電機株式会社|Information conversion method and recording / reproducing device|
    GB9314480D0|1993-07-09|1993-08-25|Hewlett Packard Co|Encoding data|
    US5450443A|1993-09-01|1995-09-12|International Business Machines Corporation|Method and apparatus for constructing asymptotically optimal second order DC-free channel codes|
    US5715355A|1994-03-19|1998-02-03|Sony Corporation|Optical disk having a particular format to store user-selected data, such as video data or computer files, including a dedicated TOC region|
    US6111528A|1995-06-07|2000-08-29|Emc Corporation|Communications arrangements for network digital data processing system|
    US6079041A|1995-08-04|2000-06-20|Sanyo Electric Co., Ltd.|Digital modulation circuit and digital demodulation circuit|
    AU4472097A|1996-10-13|1998-05-11|Sanyo Electric Co., Ltd.|Method and circuit for digital modulation and method and circuit for digital demodulation|
    TW362305B|1996-10-18|1999-06-21|Koninkl Philips Electronics Nv|Apparatus and method for converting a sequence of m-bit information words into a modulated signal|
    JPH10173537A|1996-12-10|1998-06-26|Sony Corp|Dc balance value calculation circuit for recording signal generation device|
    JP3235534B2|1997-09-24|2001-12-04|日本電気株式会社|Parallel-parallel converter, parallel-serial converter using the same, and serial-parallel converter|
    US6229462B1|1999-03-30|2001-05-08|Intel Corporation|Method and apparatus for reducing the disparity of set and clear bits on a serial line|
    KR100435215B1|1999-12-30|2004-06-09|삼성전자주식회사|Bus encoding/decoding apparatus and method|
    JP2004093462A|2002-09-02|2004-03-25|Oki Electric Ind Co Ltd|Semiconductor integrated circuit and its testing method|
    US7190653B2|2002-10-21|2007-03-13|Ricoh Company, Ltd.|Data recording/reproducing device|
    US7199741B2|2003-10-24|2007-04-03|Infineon Technologies Ag|Method for digital/analog conversion and corresponding digital/analog converter device|
    US6914545B1|2004-10-13|2005-07-05|Seiko Epson Corporation|Circuitry and methods for reducing run-length of encoded data|
    US7158057B1|2005-09-07|2007-01-02|Seiko Epson Corporation|Circuitry and methods for high speed data encoding|
    US8201071B2|2006-11-15|2012-06-12|Qimonda Ag|Information transmission and reception|
    US7786904B1|2008-11-05|2010-08-31|Mingchih Hsieh|Voltage level digital system|
    WO2010146714A1|2009-06-19|2010-12-23|富士通株式会社|Data transfer method, code conversion circuit, and device|
    US8116024B2|2009-08-10|2012-02-14|Seagate Technology Llc|Timing recovery detector|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP54142252A|JPS6367268B2|1979-11-02|1979-11-02|
    [返回顶部]